Problème decompilation d'un programme VHDL

[VampyrS]

Bonjour,

je suis en stage de fin d'étude, et je dois programmer un FPGA (Cyclone 2, 2C35) en VHDL, sur une carte Altera DE2 board.

J'ai quasiment terminé le programme, mais lors de la compilation, j'ai ce problème:

Error (10500): VHDL syntax error at SD_CARD_PICTURE.vhd(173) near text "process"; expecting "if"

Je n'ai jamais vu ce problème avant, et je voudrais savoir si quelqu'un pouvait m'aider à résoudre ce problème.

[Tortue]

Salut !
Tu peux nous mettre le code ??

[VampyrS]

-- This program is use to load picture with the SD card slot
-- then it display picture on screen with the VGA output

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;

entity SD_CARD_PICTURE is

port(
-- Clocks Input

CLOCK_27: in std_logic; -- On Board 27 MHz
CLOCK_50: in std_logic; -- On Board 50 MHz
EXT_CLOCK: in std_logic; -- External Clock

-- SRAM Interface

SRAM_DQ: inout std_logic_vector (15 downto 0); -- SRAM Data bus 16 Bits
SRAM_ADDR: out std_logic_vector (17 downto 0); -- SRAM Address bus 18 Bits
SRAM_UB_N: out std_logic; -- SRAM Low-byte Data Mask
SRAM_LB_N: out std_logic; -- SRAM High-byte Data Mask
SRAM_WE_N: out std_logic; -- SRAM Write Enable
SRAM_CE_N: out std_logic; -- SRAM Chip Enable
SRAM_OE_N: out std_logic; -- SRAM Output Enable

-- ISP1362 Interface

OTG_DATA: inout std_logic_vector (15 downto 0); -- ISP1362 Data bus 16 Bits
OTG_ADDR: out std_logic_vector (1 downto 0); -- ISP1362 Address 2 Bits
OTG_CS_N: out std_logic; -- ISP1362 Chip Select
OTG_RD_N: out std_logic; -- ISP1362 Write
OTG_WR_N: out std_logic; -- ISP1362 Read
OTG_RST_N: out std_logic; -- ISP1362 Reset
OTG_FSPEED: out std_logic; -- USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED: out std_logic; -- USB Low Speed, 0 = Enable, Z = Disable
OTG_INT0: in std_logic; -- ISP1362 Interrupt 0
OTG_INT1: in std_logic; -- ISP1362 Interrupt 1
OTG_DREQ0: in std_logic; -- ISP1362 DMA Request 0
OTG_DREQ1: in std_logic; -- ISP1362 DMA Request 1
OTG_DACK0_N: out std_logic; -- ISP1362 DMA Acknowledge 0
OTG_DACK1_N: out std_logic; -- ISP1362 DMA Acknowledge 1

-- SDRAM Interface

DRAM_DQ: inout std_logic_vector (15 downto 0); -- SDRAM Data bus 16 Bits
DRAM_ADDR: out std_logic_vector (11 downto 0); -- SDRAM Address bus 12 Bits
DRAM_LDQM: out std_logic; -- SDRAM Low-byte Data Mask
DRAM_UDQM: out std_logic; -- SDRAM High-byte Data Mask
DRAM_WE_N: out std_logic; -- SDRAM Write Enable
DRAM_CAS_N: out std_logic; -- SDRAM Column Address Strobe
DRAM_RAS_N: out std_logic; -- SDRAM Row Address Strobe
DRAM_CS_N: out std_logic; -- SDRAM Chip Select
DRAM_BA_0: out std_logic; -- SDRAM Bank Address 0
DRAM_BA_1: out std_logic; -- SDRAM Bank Address 0
DRAM_CLK: out std_logic; -- SDRAM Clock
DRAM_CKE: out std_logic; -- SDRAM Clock Enable

-- Flash Interface

FL_DQ: inout std_logic_vector (7 downto 0); -- FLASH Data bus 8 Bits
FL_ADDR: out std_logic_vector (21 downto 0); -- FLASH Address bus 22 Bits
FL_WE_N: out std_logic; -- FLASH Write Enable
FL_RST_N: out std_logic; -- FLASH Reset
FL_OE_N: out std_logic; -- FLASH Output Enable
FL_CE_N: out std_logic; -- FLASH Chip Enable

-- SD Card Interface

SD_DAT: inout std_logic; -- SD Card Data
SD_DAT3: inout std_logic; -- SD Card Data 3
SD_CMD: inout std_logic; -- SD Card Command Signal
SD_CLK: inout std_logic; -- SD Card Clock

-- USB JTAG link

TDI: in std_logic; -- CPLD -> FPGA (data in)
TCK: in std_logic; -- CPLD -> FPGA (clk)
TCS: in std_logic; -- CPLD -> FPGA (CS)
TDO: out std_logic; -- FPGA -> CPLD (data out)

-- VGA

VGA_CLK: out std_logic; -- VGA Clock
VGA_HS: out std_logic; -- VGA H_SYNC
VGA_VS: out std_logic; -- VGA V_SYNC
VGA_BLANK: out std_logic; -- VGA BLANK
VGA_SYNC: out std_logic; -- VGA SYNC
VGA_R: out std_logic_vector (9 downto 0); -- VGA Red[9:0]
VGA_G: out std_logic_vector (9 downto 0); -- VGA Green[9:0]
VGA_B: out std_logic_vector (9 downto 0) -- VGA Blue[9:0]
);

end entity;

architecture System of SD_CARD_PICTURE is

signal avs_s1_clk: std_logic;
signal avs_s1_clkevent: std_logic;
signal clk: std_logic;
signal avs_s1_chipselect: std_logic;
signal avs_s1_write: std_logic;
signal avs_s1_address: std_logic_vector (4 downto 0);
signal avs_s1_writedata: std_logic_vector (15 downto 0);
signal avs_s1_waitrequest: std_logic;
signal WRITEENABLE_TO_SRAM: std_logic;
signal ADDRESS_TO_SRAM: std_logic_vector (15 downto 0);
signal RAM_ADDR: std_logic_vector (17 downto 0);
signal RAM_WRITE_ADDR: std_logic_vector (15 downto 0);
signal WRITEDATA_TO_SRAM: std_logic_vector (15 downto 0);
signal WRITEENABLE_TO_SRAM: std_logic;
signal IMAGE_HEND: std_logic;
signal IMAGE_VEND: std_logic;
signal IMAGE_RED: std_logic_vector (9 downto 0);
signal IMAGE_GREEN: std_logic_vector (9 downto 0);
signal IMAGE_BLUE: std_logic_vector (9 downto 0);
signal READDATA_FROM_SRAM: std_logic_vector (14 downto 0);

begin

clk <= CLOCK_50/2;
avs_s1_clk <= CLOCK_50;

VGA_B <= IMAGE_BLUE;
VGA_G <= IMAGE_GREEN;
VGA_R <= IMAGE_RED;
VGA_HS <= IMAGE_HEND;
VGA_VS <= IMAGE_VEND;
SRAM_WE_N <= WRITEENABLE_TO_SRAM;
SRAM_DQ <= WRITEDATA_TO_SRAM;
SRAM_ADDR <= RAM_ADDR;


SRAM_UB_N <= '0';
SRAM_LB_N <= '0';
SRAM_CE_N <= '0';
SRAM_OE_N <= '0';

process

begin

if avs_s1_clkevent and avs_s1_clk = 1 then
if clk = 1 then -- Read Data
WRITEENABLE_TO_SRAM <= 1;
-- Tell SRAM to output data
-- NOTE: This also commits SRAM
--data that may have been
--specified during WRITE phase
ADDRESS_TO_SRAM <= RAM_ADDR;
-- Specify what address to output
else -- Write Data
if avs_s1_chipselect = 1 and avs_s1_write = 1 then
if avs_s1_address = "00000" then
-- Data Type
ADDRESS_TO_SRAM <= RAM_WRITE_ADDR;
--Tell SRAM where to write
WRITEDATA_TO_SRAM <= avs_s1_writedata;
-- Write Data
WRITEENABLE_TO_SRAM <= 0;
-- Tell SRAM to write data
elsif avs_s1_address = "00001" then
-- Address Type
RAM_WRITE_ADDR <= avs_s1_writedata;
-- Grab SRAM write ADDR
elsif avs_s1_address = "00011" then
-- Width Type
IMAGE_HEND <= avs_s1_writedata;
-- Grab Image Width
elsif avs_s1_address = "00100" then
-- Height Type
IMAGE_VEND <= avs_s1_writedata;
-- Grab Image Height
elsif avs_s1_clkevent and avs_s1_clk = 0 then
if clk = 1 then -- Latch data from SRAM
IMAGE_RED <= READDATA_FROM_SRAM(14 downto 10);
IMAGE_GREEN <= READDATA_FROM_SRAM(9 downto 5);
IMAGE_BLUE <= READDATA_FROM_SRAM(4 downto 0);
avs_s1_waitrequest <= 0;
-- Indicate that we can write data to
-- SRAM next cycle
else if clk = 0 then
avs_s1_waitrequest <= 1;
-- Indicate that we cant write data
-- to the SRAM next cycle and we need
-- to stall.

end process;

end architecture System;









J'ai pas encore fini d'affilier tous les signaux, mais je ne pense pas que ce soit ca le problème.
Sinon, je n'ai pas inventer grand chose, c'est surtout de la modification du verilog en VHDL, des différents exemples qu'on m'a fournit.

[Tortue]

Ouah...
quand je vois le code ça me fait peur. please met des tabulations, saute des lignes car c'est pas très lisible. (le prends pas mal )

Après je vois plein de trucs bizarre... genre

Code: Tout sélectionner

clk <= CLOCK_50/2;

tu veux faire quoi exactement là? diviser ta période en 2? C'est pas comme ça que ça marche si tu veux que ce soit synthetisable. Là ça doit juste passer en simulation (et encore pas sur)

Pour ton erreur de compilation, ça doit venir de là :
Tu n'as rien mis dans la liste de sensibilité

Code: Tout sélectionner

process(signal)
begin

if (signal'event and signal = 1) then
....

Après ton clkevent ça doit pas marcher c'est soit clk'event (pas sur) ou alors plus simple

Code: Tout sélectionner

if rising_edge(CLK) then

Il y a plein d'autres choses qui me choquent mais là j'ai pas trop le temps de compléter. Enfin une chose est sure, revois ton code.

Bon courage

[pulsar67]

argh...
je confirme pour "clk'event"

[VampyrS]

Merci, pour ces quelques précisions, ca va déja m'aider a avancer un peu