Error in VHDL code

[Roberto Baena]

Hi!

I've written some VHDL code and I got the following error message:

Error: Can't resolve multiple constant drivers for net sensor_sigte[1] at Simulacion_SSI.vhd(104)

Can anybody help me with this?
The code is posted below. If you need the complete program tell me and I'll send you. Of course I have posted here the part of the code I think is necessary for corrections.

Thanks!!!!!



ETAPA_ENVIO: process -- LÍNEA 104
begin
wait until (step=2);
case (sensor) is
when 1 =>
control <= "01";
sensor_sigte <= 2;
when 2 =>
control <= "10";
sensor_sigte <= 3;
when 3 =>
control <= "11";
sensor_sigte <= 1;
end case;
irq_aux <= '1';
step_sigte <= 3;
data_paralelo_out <= data_paralelo_aux;
end process;

SINCRO: process (CLK_48M, RESET)
begin

if (RESET='1') then
step <= 1;
step_sigte <= 1;
sensor <= 1;
sensor_sigte <= 1;

elsif ((CLK_48M'EVENT) AND (CLK_48M='1')) then

sensor <= sensor_sigte;
step <= step_sigte;
end if;
end process;

[JP]

Hi Roberto,

Don't you forget the process signal ?

Example:

Code: Tout sélectionner

ETAPA_ENVIO: process (clk)

JP, newbie in VHDL

[lamygale]

Hi

The cause is simple:
you have a signal that is driven in 2 process.
The VHDL cannot "understand" that.
In VHDL you must assign a signal in one and only one process.
You can read it in others process but not write in this signal.

Regards

[marsu]

Alors déja JP pour le

Code: Tout sélectionner

ETAPA_ENVIO: process (clk)

il n'est pas utile car il y a un "Wait UNTIL" et ça remplasse la liste de sensibilitée...
Le probleme vient du signal sensor_sigte qui est affecter dans les deux process. Ce n'est pas autorisé en VHDL.[/u]

[marsu]

Désole lamygale je n'avais pas vu ton message

[JP]

il n'est pas utile car il y a un "Wait UNTIL" et ça remplasse la liste de sensibilitée...

Ok merci pour l'info

JP, toujours newbie mais il se soigne