vhdl

[vhdl]

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_signed.all;
USE IEEE.std_logic_arith.all;

ENTITY fibo IS

port( clk,raz,en : in std_logic;
n: in std_logic_vector (7 downto 0);
qc : out std_logic_vector (15 downto 0);
ovf : out std_logic
);

END fibo;

ARCHITECTURE behavioral OF fibo IS
-- signal Previous : natural:=1;
-- signal Current : natural:=1;
--signal Next_Fib : natural;
BEGIN

--Next_Fib<=Current+Previous ;

PROCESS (clk)
variable Previous : integer:=1;
variable Current : integer:=1;
variable Next_Fib : integer:=2;
VARIABLE cnt : integer:=0;
BEGIN
IF(clk'event AND clk='1') then

IF raz = '1' THEN

Previous := 1;
Current := 1;
cnt:=0;

ELSIF en='1' THEN

Previous := Current;
Current := Next_Fib;
Next_Fib :=Current+Previous ;

cnt:=cnt+1;

IF(cnt>24) then
ovf<='1';
else
ovf<='0';
END IF;

IF(cnt = n) THEN

Previous := 1;
Current := 1;
cnt:=0;

END IF;

END IF;

qc <= CONV_STD_LOGIC_VECTOR(Previous,16);
END IF;


END PROCESS;

END behavioral;