un gros problème en VHDL : je n'arrive pas à faire une pauvre addition 'alors que dans un autre exercice à coté, ca fonctionne nickel)
en gros, voila les endroits concernés :
multiplicand : in std_logic;
multiplier : in std_logic;
Signal x : std_logic_vector(7 downto 0);
Signal y : std_logic_vector(7 downto 0);
Signal z : std_logic_vector(7 downto 0);
variable n : integer := 0;
x(n) <= multiplicand;
y(n) <= multiplier;
z <= z + (x(n) and y(0));
et quelque-soit els trucs que je fait, z reste égal à 0
pour le code complet :
- Code: Tout sélectionner
-- ***** 8 bits Sequential Multiplier *****
-- ********** with serial inputs **********
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-- **** entity definition ****
entity MulKeulSerial is
Port ( clock : in std_logic;
start : in std_logic;
multiplicand : in std_logic;
multiplier : in std_logic;
result : out std_logic;
test1 : out std_logic;
test2 : out std_logic;
test3 : out std_logic;
test4 : out std_logic;
ready : out std_logic);
end MulKeulSerial;
-- **** architecture definition ****
architecture RTL of MulKeulSerial is
Signal x : std_logic_vector(7 downto 0);
Signal y : std_logic_vector(7 downto 0);
Signal z : std_logic_vector(7 downto 0);
begin
process(clock, start)
variable n : integer := 0;
begin
if (rising_edge(start)) then
x <= "00000000";
y <= "00000000";
z <= "00000000";
n := 0;
ready <= '0';
elsif (rising_edge(clock)) then
n := 0;
if (n < 8) then
x(n) <= multiplicand;
y(n) <= multiplier;
z <= z + (x(n) and y(0));
test1<=z(0);
test2<=z(1);
test3<=z(2);
test4<=z(3);
if(n >= 1) then
z <= z + (x(n-1) and y(1)); end if;
if(n >= 2) then
z <= z + (x(n-2) and y(2)); end if;
if(n >= 3) then
z <= z + (x(n-3) and y(3)); end if;
if(n >= 4) then
z <= z + (x(n-4) and y(4)); end if;
if(n >= 5) then
z <= z + (x(n-5) and y(5)); end if;
if(n >= 6) then
z <= z + (x(n-6) and y(6)); end if;
if(n >= 7) then
z <= z + (x(n-7) and y(7)); end if;
end if;
result <= z(0);
--z <= srl shift right logical(z); dosen't work, use that instead
z(0)<=z(1);z(1)<=z(2);z(2)<=z(3);z(3)<='0';
n := n + 1;
if(n > 7 and z = "00000000") then
ready <= '1';
end if;
end if;
end process;
end RTL;
